The SN74HC175N is a quadruple D-type Flip-flop with clear. It has a direct clear (CLR\) input. It features complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of clock. When clock is at either the high or low level, the D input has no effect at the output.

• Outputs can drive up to 10 LSTTL loads
• Contain four flip-flops with double-rail outputs
• 80µA Maximum low power consumption
• 13ns Typical tpd
• ±4mA Output drive at 5V
• 1µA Maximum low input current