2: 8 universal output clock buffer for use at wireless infrastructure radio, driving arrays of DSP, ADC / DAC or high-performance PHY / SerDes, wired communication system digital system boards and clock distribution.

• 2 clock inputs with input source switch
• Flexible standard component with high frequency up to 3GHz
• Low additive phase noise and excellent channel isolation
• Integrated LDO for best supply noise rejection
• Low additive noise clock distribution has low impact on SNR budget
• Low skew outputs maintain clock synchronization

Полупроводники - Микросхемы\Таймеры, Генераторы и Управление Частотой\Генераторы и Формироваетли Тактовых Сигналов

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